
% LocalWords:  Heterojunction FETs TFETs sub-threshold CMOS FinFET TFET HTFET
% LocalWords:  optimizations tradeoffs

The existence of domains where traditional CMOS processors are
inefficient has been well-documented in the current literature. In
particular, the inefficiency of general purpose CMOS designs operating
at very low supply voltages is well-known, and steep sub-threshold
slope technologies, such as Tunneling Field Effect Transistors (TFETs), have been demonstrated
as a viable alternative for the low-voltage operation domain. However,
restricting the design space of steep slope technology-based
processors to near-threshold or sub-threshold general purpose
processors does the technology a disservice.  

Steep slope (SS) architectures can
simultaneously expand the frontiers of viable computers at both ends
of the energy scale: On the one hand, SS architectures enable
ultra-low power sensor nodes and wearable technology, while on the
other, they are applicable to high powered servers and high
performance computing engines.  We demonstrate the benefits of
adapting this technology in such non-conventional domains, while
attempting to address the major challenges encountered. We explore the
effect of noise and variations at various levels of abstraction,
ranging from the device to the architecture, and examine various
techniques to overcome them.

